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INTEGRATED CIRCUITS
DATA SHEET
SAA7184; SAA7185B Digital Video Encoders (DENC2-M6)
Preliminary specification Supersedes data of 1995 Nov 14 File under Integrated Circuits, IC22 1996 Jul 03
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
FEATURES * CMOS 5 V device * Digital PAL/NTSC encoder * System pixel frequency 13.5 MHz * Accepts MPEG decoded data * 8-bit wide MPEG port * Input data format Cb, Y, Cr etc. (CCIR 656) * 16-bit wide YUV input port * I2C-bus control port or alternatively MPU parallel control port * Encoder can be master or slave * Programmable horizontal and vertical input synchronization phase * Programmable horizontal sync output phase * OVL overlay with Look-Up Tables (LUTs) 8 x 3 bytes * Colour bar generator * Line 21 closed caption encoder * Cross-colour reduction * Macrovision revision_6 Pay-per-View copy protection system as option (SAA7184 only). Remark: This device is protected by U.S. patent numbers 4631603 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anticopy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information. * DACs operating at 27 MHz with 10-bit resolution * Controlled rise and fall times of output syncs and blanking * Down-mode of DACs * CVBS and S-Video output simultaneously * PLCC68 package. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7184WP SAA7185BWP PLCC68 DESCRIPTION plastic leaded chip carrier; 68 leads
SAA7184; SAA7185B
GENERAL DESCRIPTION The SAA7184 and SAA7185B digital video encoders 2 (DENC2-M6) encode digital YUV video data to an NTSC or PAL CVBS or S-Video signal. The circuit accepts CCIR compatible YUV data with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG decoded data. The device includes a sync/clock generator and on-chip Digital-to-Analog Converters (DACs). The circuit is compatible to the DIG-TV2 chip family.
VERSION SOT188-2
1996 Jul 03
2
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
QUICK REFERENCE DATA SYMBOL VDDA VDDD IDDA IDDD Vi Vo(p-p) RL ILE DLE Tamb analog supply voltage digital supply voltage analog supply current digital supply current input signal voltage levels analog output signal voltages Y, C and CVBS without load - (peak-to-peak value) load resistance LF integral linearity error LF differential linearity error operating ambient temperature 80 - - 0 PARAMETER
SAA7184; SAA7185B
MIN. 4.75 4.5 - -
TYP. 5.0 5.0 50 130 2 - - - -
MAX. 5.25 5.5 55 170 - - 2 1 +70 V V
UNIT
mA mA V V LSB LSB C
TTL compatible
BLOCK DIAGRAM
KEY SEL_ED 18 MP7 to MP0 VP0 to VP7 20 to 27 8 9 to 16 8
OVL0 to OVL2 32 to 34
RTCI 43
VDDD1 to VDDD3 17,37,67
VDDA1 to VrefH VDDA4 IOA 47 55 48,50, 54,56 53 A 51 D 49 52 46
31
DATA MANAGER
ENCODER
OUTPUT INTERFACE
CVBS Y CHROMA VSSA VrefL
8
8 internal control bus
8
RCM1 RCM2
29 8 30 8 clock timing signals 8
SAA7184 SAA7185B
CONTROL INTERFACE
SYNC CLK
1,8,19 28,35, 42,62
63 to 66 2 to 5
68
61
59
60
58
57
41 XTALI
40
38 LLC
39
36
6
7
MGC679
VSSD1 to VSSD7
DP0 to DP7
CSN/SA
A0/SDA
RES
CDIR
RCV2
SEL_MPU
RWN/SCL
DTACK
XTALO
CREF
RCV1
Fig.1 Block diagram.
1996 Jul 03
ll pagewidth
3
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
PINNING SYMBOL VSSD1 DP4 to DP7 PIN 1 2 to 5 I/O - I/O digital ground 1
SAA7184; SAA7185B
DESCRIPTION Upper 4 bits of the data port; if pin 68 (SEL_MPU) is HIGH, the data bus of the parallel MPU interface is used. If pin 68 is LOW, then the UV lines of the video port are used. Raster control 1 for video port; depending on the synchronization mode, this pin receives or provides a VS/FS/FSEQ signal. Raster control 2 for video port; depending on the synchronization mode, this pin receives or provides an HS/HREF/CBL signal. digital ground 2 Video port; this is an input for CCIR 656 compatible multiplexed video data. If the 16-bit DIG-TV2 format is used, then Y data is input. digital supply voltage 1 select encoder data; selects input data either from the MPEG port or from the video port digital ground 3 MPEG port; it is an input for CCIR 656 style multiplexed YUV data. digital ground 4 Raster control 1 for MPEG port; this pin provides a VS/FS/FSEQ signal. Raster control 2 for MPEG port; this pin provides an HS pulse for the MPEG decoder. key signal for OVL (active HIGH) on-screen display data; this is the index for the internal OVL look-up tables digital ground 5 Clock direction; if the CDIR input is HIGH, the circuit receives a clock signal, if not LLC and CREF are generated by the internal crystal oscillator. digital supply voltage 2 Line-locked clock; this is the 27 MHz master clock for the encoder. The direction is set by the CDIR pin. Clock reference signal; this is the clock qualifier for DIG-TV2 compatible signals. The polarity is programmable by software. crystal oscillator output (to crystal) Crystal oscillator input (from crystal). If the oscillator is not used, this pin should be connected to ground. digital ground 6 Real time control Input; if the clock is provided by the SAA7151B or SAA7111, RTCI should be connected to the RTCO pin of the decoder to improve the signal quality. test pin (should be connected to digital ground for normal operation) test pin (should be connected to digital ground for normal operation) lower reference voltage input for the DACs upper reference voltage input for the DACs analog positive supply voltage 1 for the DACs and output amplifiers
RCV1 RCV2 VSSD2 VP0 to VP7 VDDD1 SEL_ED VSSD3 MP7 to MP0 VSSD4 RCM1 RCM2 KEY OVL0 to OVL2 VSSD5 CDIR VDDD2 LLC CREF XTALO XTALI VSSD6 RTCI
6 7 8 9 to 16 17 18 19 20 to 27 28 29 30 31 32 to 34 35 36 37 38 39 40 41 42 43
I/O I/O - I I I - I - O O I I - I I I/O I/O O I - I
AP SP VrefL VrefH VDDA1
44 45 46 47 48
- - I I I
1996 Jul 03
4
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
SYMBOL CHROMA VDDA2 Y VSSA CVBS VDDA3 IOA VDDA4 RES DTACK RWN/SCL A0/SDA CSN/SA
PIN 49 50 51 52 53 54 55 56 57 58 59 60 61
I/O O I O - O I I I I O I I/O I
DESCRIPTION analog output of the chrominance signal analog supply voltage 2 for the DACs and output amplifiers analog output of the luminance signal analog ground for the DACs and output amplifiers analog output of the CVBS signal analog supply voltage 3 for the DACs and output amplifiers current input for the output amplifiers (connected via a 15 k resistor to VDDA) analog supply voltage 4 for the DACs and output amplifiers Reset input, active LOW. After reset is applied, all outputs are in 3-state input mode. The I2C-bus receiver waits for the start condition. Data acknowledge output of the parallel MPU interface, active LOW, otherwise high impedance. If pin 68 (SEL_MPU) is HIGH, this is the read/write signal of the parallel MPU interface. Otherwise it is the I2C-bus serial clock input. If pin 68 (SEL_MPU) is HIGH, this is the address signal of the parallel MPU interface. Otherwise it is the I2C-bus serial data input/output. If pin 68 (SEL_MPU) is HIGH, this is the chip select signal of the parallel MPU interface. Otherwise it is the I2C-bus slave address select pin. When LOW slave address = 88H, when HIGH slave address = 8CH. digital ground 7 Lower 4 bits of the data port; if pin 68 (SEL_MPU) is HIGH, the data bus of the parallel MPU interface is used. If pin 68 is LOW, then the UV lines of the video port are used. digital supply voltage 3 Select MPU interface input; if it is HIGH, the parallel MPU interface is active, if not the I2C-bus interface will be used.
VSSD7 DP0 to DP3
62 63 to 66
- I/O
VDDD3 SEL_MPU
67 68
I I
1996 Jul 03
5
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
59 RWN/SCL
60 A0/SDA
handbook, full pagewidth
49 CHROMA
58 DTACK
56 VDDA4
54 VDDA3
50 VDDA2
48 VDDA1
VrefH
52 VSSA
53 CVBS
57 RES
55 IOA
VrefL
45 SP
CSN/SA 61 VSSD7 62 DP0 63 DP1 64 DP2 65 DP3 66 VDDD3 67 SEL_MPU 68 VSSD1 1 DP4 DP5 DP6 DP7 2 3 4 5
44 AP
51 Y
47
46
43 RTCI 42 VSSD6 41 XTALI 40 XTALO 39 CREF 38 LLC 37 VDDD2 36 CDIR
SAA7184 SAA7185B
35 VSSD5 34 OVL2 33 OVL1 32 OVL0 31 KEY 30 RCM2 29 RCM1 28 VSSD4 27 MP0
RCV1 6 RCV2 VSSD2 VP0 7 8 9
VP1 10
VP2 11
VP3 12
VP4 13
VP5 14
VP6 15
VP7 16
VDDD1 17
SEL_ED 18
VSSD3 19
MP7 20
MP6 21
MP5 22
MP4 23
MP3 24
MP2 25
MP1 26
MGC678
Fig.2 Pin configuration.
1996 Jul 03
6
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
FUNCTIONAL DESCRIPTION The digital MPEG-compatible video encoder (DENC2-M6) encodes digital luminance and chrominance into analog CVBS and S-Video (Y/C) signals simultaneously. NTSC-M and PAL B/G standards and sub-standards are also supported. The basic encoder function consists of subcarrier generation and colour modulation plus insertion of synchronization signals. Luminance and chrominance signals are filtered in accordance with the standard requirements of RS-170-A and CCIR 624. For ease of analog post filtering the signals are twice oversampled, with respect to the pixel clock, before digital-to-analog conversion. For total filter transfer characteristics see Figs 3, 4, 5 and 6. The DACs are realized with full 10-bit resolution. The encoder provides three 8-bit wide data ports that serve different applications. The MPEG port and the video port accept 8 lines multiplexed Cb-Y-Cr data. The video port is also able to accommodate DIG-TV2 family compatible 16-bit YUV signals. In this event, the data port is used for the U/V components. Alternatively, the data port can accommodate the data of an 8-bit wide microprocessor interface. The 8-bit multiplexed Cb-Y-Cr formats are CCIR 656 (D1 format) compatible, but the SAV, EAV etc. codes are not decoded. A crystal-stable master clock (LLC) of 27 MHz, which is twice the CCIR line-locked pixel clock frequency of 13.5 MHz, needs to be supplied externally. A crystal oscillator input/output pair of pins and an on-chip clock driver are provided optionally. It is also possible to connect the Philips Digital Video Decoder (SAA7111 or SAA7151B) in conjunction with a CREF clock qualifier to the DENC2-M6 via the RETCI pin (connected to RTCO) of a decoder. Information concerning the actual subcarrier, PAL-ID and (with SAA7111) definite subcarrier phase can be inserted. The DENC2-M6 synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals, from that clock. The DENC2-M6 is always the timing master for the MPEG port but can also be configured as master or slave for the video port.
SAA7184; SAA7185B
The IC also contains closed caption and extended data services encoding (line 21), and supports anti-taping signal generation in accordance with Macrovision. It also supports OVL via KEY and 3-bit overlay techniques using a 24 x 8 LUT. The IC can be programmed via the I2C-bus or via the 8-bit MPU interface, but only one interface configuration can be active at a time. If the 16-bit video port mode (VP and DP) is being used, only the I2C-bus interface can be selected. A number of possibilities are provided for setting the different video parameters such as: black and blanking level control colour subcarrier frequency black variable burst amplitude etc. During reset (RES = LOW) and after reset is released, all digital I/O stages are set to the input mode. A reset forces the control interfaces to abort any running bus transfer and to set register 3AH to contents 1FH, register 61H to contents 06H, and registers 6CH and 7AH to contents 00H. All other control registers are not influenced by a reset. Data manager Real time arbitration on the data stream to be encoded is performed in the data manager. Depending on the hardware conditions (signals on pins SEL_ED, KEY, OVL2 to OVL0, MP7 to MP0, VP7 to VP0 and DP7 to DP0) and different software programming, either data from the MP port, from the VP port or from the OVL port, is selected to be encoded to CVBS and Y/C signals. Optionally, the OVL colour look-up tables located in this block can be read out in a pre-defined sequence (8 steps per active video line) thereby achieving, for example, a colour bar test pattern generator without the need for an external data source. The colour bar function is only under software control. Encoder VIDEO PATH The encoder generates luminance and colour subcarrier output signals, suitable for use as CVBS or separate Y/C signals, from the Y, U and V baseband signals.
1996 Jul 03
7
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
The luminance gain and offset are modified (offset being programmable within a certain range to enable different black level set-ups). After the signals have been inserted, a fixed synchronization level in accordance with standard composite synchronization schemes and blanking level, (also programmable in a certain range to allow for manipulations with Macrovision anti-tapping) additional insertion of AGC super white pulses (programmable in height) is supported. In order to enable easy analog post filtering, luminance is interpolated from a 13.5 MHz data rate to a 27 MHz data rate, thereby providing luminance in a 10-bit resolution. This filter is also used to define smoothed transients for synchronization pulses and blanking period. The transfer characteristics of the luminance interpolation filter are illustrated in Figs 5 and 6. The chrominance gain is modified (programmable separately for U and V), a standard dependent burst is inserted before baseband colour signals are interpolated from a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be bypassed, thereby providing a higher colour bandwidth, which can be used for the Y/C output. The transfer characteristics of the chrominance interpolation filter are illustrated in Figs 3 and 4. The amplitude of the inserted burst is programmable within a certain range, suitable for standard signals and for special effects. Colour in a 10-bit resolution is provided on the subcarrier after the succeeding quadrature modulator. The numeric ratio between Y and C outputs is in accordance with set standards. CLOSED CAPTION ENCODER Using the closed caption encoder circuit, data in accordance with the specification of closed caption or extended data service, delivered by the control interface, can be encoded (line 21). Two dedicated pairs of bytes (two bytes per field) are possible, each pair preceded by run-in clocks and framing code. The actual line number where data is to be encoded, can be modified within a certain range. The data clock frequency is in accordance with the definition for NTSC-M standard 32 times horizontal line frequency. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE.
SAA7184; SAA7185B
It is also possible to encode closed caption data for 50 Hz field frequencies at 32 times horizontal line frequency. Output interface In the output interface, encoded Y and C signals are converted from digital to analog in a 10-bit resolution and then combined into a 10-bit CVBS signal. Also, in front of the summation point, the luminance signal can be fed through a further filter stage (optional), thereby suppressing components in the subcarrier frequency range. Thus, a type of cross colour reduction is provided, which is useful in a standard TV set with CVBS input. The slopes of the synchronization pulses are not affected with any active cross colour reduction. Three different filter characteristics or bypass are available, see Fig.5. The CVBS output occurs with the same processing delay as the Y and C outputs. Absolute amplitudes at the input of the DAC for CVBS is reduced by 1516 with respect to Y and C DACs to make maximum use of conversion ranges. Outputs of all DACs can be set together, via software control, to minimum output voltage for either purpose. Synchronization The synchronization of the DENC2 is able to operate in two modes; slave mode and master mode. In the slave mode, the circuit accepts synchronization pulses at the bidirectional RCV1 port. The timing and trigger behaviour, related to the video signal on VP (and DP, if used), can be influenced by programming the polarity and on-chip delay of RCV1. The active slope of RCV1 defines the vertical phase and, as an option, the odd/even and colour frame phase to be initialized. It can also be used to set the horizontal phase. If the horizontal phase is not to be influenced by RCV1, a horizontal pulse needs to be applied at pin RCV2. Timing and trigger behaviour can also be influenced for RCV2. If there are missing pulses at RCV1 and/or RCV2, the time base of the DENC2-M6 will become free-running, thus an arbitrary number of synchronization slopes may miss, but no additional pulses must occur (such as with wrong phase). If the vertical and horizontal phase is derived from RCV1, RCV2 can be used for horizontal or composite blanking input or output.
1996 Jul 03
8
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
In the master mode, the time base of the circuit is continuously free-running. At the RCV1 port, the IC can output: * A vertical sync signal (VS) with 3 or 2.5 lines duration, or * An odd/even signal which is LOW in odd fields, or * A field sequence signal (FSEQ) which is HIGH in the first of 4 respectively 8 fields. The IC can provide a horizontal pulse with programmable start and stop phase at the RCV2 port. This pulse can be inhibited in the vertical blanking period to build up, for example, a composite blanking signal. The phase of the output pulses at RCV1 or RCV2 are referenced to the VP port, polarity of both signals is selectable. The DENC2-M6 is always the timing master for the source at the MP input. The IC provides two signals for synchronizing this source: 1. At the RCM1 port the same signals as at RCV1 (as output) are available. 2. At RCM2 the IC provides a horizontal pulse with programmable start and stop phase. The start and end of the active part can be programmed. The active part of a field always starts at the beginning of a line if the standard blanking option SBLBN is not set. Control interface DENC2-M6 contains two control interfaces, an I2C-bus slave transceiver and an 8-bit parallel microprocessor interface. The interfaces cannot be used simultaneously. The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write only, except one status byte which can be read. Two I2C-bus slave addresses can be selected (pin SEL_MPU must be LOW): 88H: pin 61 = LOW 8CH: pin 61 = HIGH.
SAA7184; SAA7185B
The parallel interface is defined by: D7 to D0 data bus CS active LOW chip select signal RW read/write signal, LOW for a write cycle DTACK 680xx style data acknowledge (handshake), active-LOW A0 register select, LOW selects address, HIGH selects data. The parallel interface uses two registers, one auto-incremental containing the current address of a control register (equals subaddress with I2C-bus control), and one containing actual data. The currently addressed register is mapped to the corresponding control register. The status byte can be read (optionally) via a read access to the address register, no other read access is provided. Input levels and formats DENC2-M6 accepts digital YUV data with levels (digital codes) in accordance with CCIR 601. Deviating amplitudes in the colour difference signals can be compensated for by independent gain control setting, while the gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. The MPEG port accepts only 8-bit multiplexed CCIR 656 compatible data. If the I2C-bus interface is used, the VP port can accommodate both formats, 8-bit multiplexed Cb-Y-Cr data on the VP lines, or the 16-bit DTV2 format with the Y signal on the VP lines and the UV signal on the DP port. Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation.
1996 Jul 03
9
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
Table 1 CCIR signal component levels IRE 0 Y 50 100 bottom peak Cb colourless top peak bottom peak Cr colourless top peak Table 2 8-bit multiplexed format (similar to CCIR 656) TIME Sample Luminance pixel number Colour pixel number Table 3 16-bit multiplexed format (DTV2 format) TIME Sample Y line Sample UV line Luminance pixel number Colour pixel number 0 Y0 Cb0 0 0 1 2 Y1 Cr0 1 3 0 Cb0 0 0 1 Y0 2 Cr0 1 2 Y1 DIGITAL LEVEL 16 126 235 16 128 240 16 128 240
SAA7184; SAA7185B
SIGNAL
CODE straight binary
straight binary
straight binary
4 Cb2 2
5 Y2 2
6 Cr2 3
7 Y3
4 Y2 Cb2 2
5
6 Y3 Cr2 3 2
7
1996 Jul 03
10
Bit allocation map
Table 4 DATA BYTE (note 1) D7 0 0 CBENB OVLY07 OVLU07 OVLV07 OVLY77 OVLU77 OVLV77 CHPS7 GAINU7 GAINV7 GAINU8 GAINV8 0 0 DECTYP FSC07 FSC15 FSC23 FSC31 L21O07 L21O17 L21E07 L21E17 MODIN1 SRCV11 L21O16 L21E06 L21E16 MODIN0 SRCV10 L21O06 FSC30 FSC22 FSC14 FSC13 FSC21 FSC29 L21O05 L21O15 L21E05 L21E15 PCREF TRCV2 FSC06 FSC05 BSTA6 BSTA5 DOWN INPI1 YGS BSTA4 FSC04 FSC12 FSC20 FSC28 L21O04 L21O14 L21E04 L21E14 SCCLN4 ORCV1 0 0 0 0 BLNNL5 BLNNL4 0 BLCKL5 BLCKL4 GAINV6 GAINV5 GAINV4 GAINV3 BLCKL3 BLNNL3 0 RTCE BSTA3 FSC03 FSC11 FSC19 FSC27 L21O03 L21O13 L21E03 L21E13 SCCLN3 PRCV1 GAINU6 GAINU5 GAINU4 GAINU3 CHPS6 CHPS5 CHPS4 CHPS3 OVLV76 OVLV75 OVLV74 OVLV73 CHPS2 GAINU2 GAINV2 BLCKL2 BLNNL2 0 SCBW BSTA2 FSC02 FSC10 FSC18 FSC26 L21O02 L21O12 L21E02 L21E12 SCCLN2 CBLF OVLU76 OVLU75 OVLU74 OVLU73 OVLU72 OVLV72 OVLY76 OVLY75 OVLY74 OVLY73 OVLY72 OVLY71 OVLU71 OVLV71 CHPS1 GAINU1 GAINV1 BLCKL1 BLNNL1 0 PAL BSTA1 FSC01 FSC09 FSC17 FSC25 L21O01 L21O11 L21E01 L21E11 SCCLN1 ORCV2 OVLY70 OVLU70 OVLV70 CHPS0 GAINU0 GAINV0 BLCKL0 BLNNL0 0 FISE BSTA0 FSC00 FSC08 FSC16 FSC24 L21O00 L21O10 L21E00 L21E10 SCCLN0 PRCV2 OVLV06 OVLV05 OVLV04 OVLV03 OVLV02 OVLV01 OVLU06 OVLU05 OVLU04 OVLU03 OVLU02 OVLU01 OVLY06 OVLY05 OVLY04 OVLY03 OVLY02 OVLY01 0 0 V656 VY2C VUV2C MY2C 0 0 0 0 0 0 0 MUV2C OVLY00 OVLU00 OVLV00 0 0 0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0
1996 Jul 03
Slave receiver (slave address 88h or 8Ch)
REGISTER FUNCTION
SUB ADDRESS
Null
00
Philips Semiconductors
Null
39
Input port control
3A
OVL LUT Y0
42
OVL LUT U0
43
OVL LUT V0
44
OVL LUT Y7
57
OVL LUT U7
58
Digital Video Encoders (DENC2-M6)
OVL LUT V7
59
Chrominance phase
5A
11
Gain U
5B
Gain V
5C
Gain U MSB, black level
5D
Gain V MSB, blanking level
5E
Null
60
Standard control
61
Burst amplitude
62
Subcarrier 0
63
Subcarrier 1
64
Subcarrier 2
65
Subcarrier 3
66
Line 21 odd 0
67
Line 21 odd 1
68
Line 21 even 0
69
Line 21 even 1
6A
SAA7184; SAA7185B
Encoder control, CC line
6B
Preliminary specification
RCV port control
6C
DATA BYTE (note 1) D7 0 HTRIG7 HTRIG8 PHRES1 BMRQ7 EMRQ7 0 0 0 0 BRCV7 ERCV7 0 0 FAL7 LAL7 0 0 LAL8 FAL8 0 LAL6 LAL5 LAL4 LAL3 FAL6 FAL5 FAL4 FAL3 0 0 0 0 0 FAL2 LAL2 0 ERCV10 ERCV09 ERCV08 0 BRCV10 ERCV6 ERCV5 ERCV4 ERCV3 ERCV2 BRCV6 BRCV5 BRCV4 BRCV3 BRCV2 0 0 0 0 0 0 BRCV1 ERCV1 BRCV09 FLC1 FAL1 LAL1 0 0 0 0 0 0 0 0 0 0 0 0 0 EMRQ10 EMRQ09 EMRQ08 0 BMRQ10 BMRQ09 EMRQ6 EMRQ5 EMRQ4 EMRQ3 EMRQ2 EMRQ1 BMRQ6 BMRQ5 BMRQ4 BMRQ3 BMRQ2 BMRQ1 BMRQ0 EMRQ0 BMRQ08 0 0 0 BRCV0 ERCV0 BRCV08 FLC0 FAL0 LAL0 0 PHRES0 SBLBN VTRIG4 VTRIG3 VTRIG2 VTRIG1 VTRIG0 HTRIG9 HTRIG10 0 0 0 0 0 HTRIG6 HTRIG5 HTRIG4 HTRIG3 HTRIG2 HTRIG1 HTRIG0 0 0 0 SRCM11 SRCM10 CCEN1 CCEN0 D6 D5 D4 D3 D2 D1 D0
REGISTER FUNCTION
SUB ADDRESS
1996 Jul 03
RCM, CC mode
6D
Horizontal trigger
6E
Horizontal trigger
6F
Philips Semiconductors
fsc reset mode, Vertical trigger
70
Begin MP request
71
End MP request
72
MSBs MP request
73
Null
74
Null
75
Null
76
Begin RCV2 output
77
End RCV2 output
78
Digital Video Encoders (DENC2-M6)
MSBs RCV2 output
79
Field length
7A
12
First active line
7B
Last active line
7C
MSBs field control
7D
Note
1. All bits labelled `0' are reserved. They must be programmed with logic 0.
SAA7184; SAA7185B
Preliminary specification
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
I2C-bus format Table 5 S Table 6 I2C-bus address; see Table 6 SLAVE ADDRESS ACK SUBADDRESS ACK DATA 0 ACK
SAA7184; SAA7185B
--------
DATA n
ACK
P
Explanation of Table 5 PART DESCRIPTION START condition 1 0 0 0 1 0 0 X or 1 0 0 0 1 1 0 X (note 1) acknowledge, generated by the slave subaddress byte data byte continued data bytes and ACKs STOP condition
S Slave address ACK Subaddress (note 2) DATA -------P Notes
1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read, no subaddressing with read. 2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed. Slave Receiver Table 7 Subaddress 3A LOGIC LEVEL 0 1 MY2C VUV2C VY2C V656 CBENB 0 1 0 1 0 1 0 1 0 1 DESCRIPTION Cb/Cr data at MP is two's complement. Cb/Cr data at MP is straight binary. Default after reset. Y data at MP is two's complement. Y data at MP is straight binary. Default after reset. Cb/Cr data input to VP or DP is two's complement Cb/Cr data input to VP or DP is straight binary. Default after reset. Y data input to VP is two's complement Y data input to VP is straight binary. Default after reset. selects YUV 422 format on VP (8 lines Y) and DP (8 lines multiplexed Cb/Cr). selects CCIR 656 compatible format on VP (8 lines Cb, Y, Cr). Default after reset. data from input ports is encoded. Default after reset. colour bar with programmable colours (entries of OVL_LUTs) is encoded. The LUTs are read in upward order from index 0 to index 7.
DATA BYTE MUV2C
1996 Jul 03
13
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
Table 8 Subaddress 42 to 59 DATA BYTE(1) COLOUR OVLY White Yellow Cyan Green Magenta Red Blue Black 107 (6BH) 107 (6BH) 82 (52H) 34 (22H) 42 (2AH) 03 (03H) 17 (11H) 240 (F0H) 234 (EAH) 212 (D4H) 209 (D1H) 193 (C1H) 169 (A9H) 163 (A3H) 144 (90H) 144 (90H) Notes OVLU 0 (00H) 0 (00H) 144 (90H) 172 (ACH) 38 (26H) 29 (1DH) 182 (B6H) 200 (C8H) 74 (4AH) 56 (38H) 218 (DAH) 227 (E3H) 112 (70H) 84 (54h) 0 (00H) 0 (00H) OVLV
SAA7184; SAA7185B
INDEX(2) 0 (00H) 0 (00H) 18 (12H) 14 (0EH) 144 (90H) 172 (ACH) 162 (A2H) 185 (B9H) 94 (5EH) 71 (47H) 112 (70H) 84 (54H) 238 (EEH) 242 (F2H) 0 (00H) 0 (00H) 7 6 5 4 3 2 1 0
1. Contents of OVL look-up tables. All 8 entries are 8-bits. Data representation is in accordance with CCIR 601 (Y, Cb, Cr), but two's complement, e.g. for a 100100 (upper number) or 10075 (lower number) colour bar. 2. For normal colour bar with CBENB = logic 1. Table 9 Subaddress 5A DESCRIPTION phase of encoded colour subcarrier (including burst) relative to horizontal sync. Can be adjusted in steps of 360/256 degrees.
DATA BYTE CHPS
Table 10 Subaddress 5B and 5D DATA BYTE GAINU DESCRIPTION CONDITIONS IRE(1) output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal REMARKS
variable gain for Cb signal; white-to-black = 92.5 input representation in GAINU = 0 accordance with GAINU = 118 (76H) "CCIR 601" white-to-black = 100 IRE(2) GAINU = 0 GAINU = 125 (7DH)
Notes 1. GAINU = -2.17 x nominal to +2.16 x nominal. 2. GAINU = -2.05 x nominal to +2.04 x nominal.
1996 Jul 03
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Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
Table 11 Subaddress 5C and 5E DATA BYTE GAINV DESCRIPTION variable gain for Cr signal; input representation in accordance with "CCIR 601" CONDITIONS white-to-black = 92.5 IRE(1) GAINV = 0 GAINV = 165 (A5H) white-to-black = 100 GAINV = 0 GAINV = 175 (AFH) Notes 1. GAINV = -1.55 x nominal to + 0.55 x nominal. 2. GAINV = -1.46 x nominal to + 0.46 x nominal. Table 12 Subaddress 5D DATA BYTE BLCKL DESCRIPTION variable black level; input representation in accordance with "CCIR 601" CONDITIONS white-to-sync = 140 IRE(1) BLCKL = 0 BLCKL = 63 (3FH) white-to-sync = 143 IRE(2) BLCKL = 0 BLCKL = 63 (3FH) Notes IRE(2)
SAA7184; SAA7185B
REMARKS output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal output subcarrier of V contribution = 0 output subcarrier of V contribution = nominal
REMARKS output black level = 24 IRE output black level = 49 IRE output black level = 24 IRE output black level = 50 IRE
1. Output black level/IRE = BLCKL x 25/63 + 24; recommended value: BLCKL = 60 (3CH) normal. 2. Output black level/IRE = BLCKL x 26/63 + 24; recommended value: BLCKL = 45 (2DH) normal. Table 13 Subaddress 5E DATA BYTE BLNNL DESCRIPTION variable blanking level CONDITIONS white-to-sync = 140 IRE(1) BLNNL = 0 BLNNL = 63 (3FH) white-to-sync = 143 IRE(2) BLNNL = 0 BLNNL = 63 (3FH) Notes 1. Output black level/IRE = BLNNL x 25/63 + 17; recommended value: BLNNL = 58 (3AH) normal. 2. Output black level/IRE = BLNNL x 26/63 + 17; recommended value: BLNNL = 63 (3FH) normal. output blanking level = 17 IRE output blanking level = 43 IRE output blanking level = 17 IRE output blanking level = 42 IRE REMARKS
1996 Jul 03
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Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
Table 14 Subaddress 5F (CCRS and BLNVB; note 1) DATA BYTE FUNCTION CCRS1 0 0 1 1 Note CCRS0 0 1 0 1
SAA7184; SAA7185B
no cross colour reduction (for overall transfer characteristic of luminance see Fig.5) cross colour reduction #1 active (for overall transfer characteristic see Fig.5) cross colour reduction #2 active (for overall transfer characteristic see Fig.5) cross colour reduction #3 active (for overall transfer characteristic see Fig.5)
1. BLNVB = vertical blanking level during vertical blanking interval and its value is typically identical to BLNNL. Table 15 Subaddress 61 DATA BYTE FISE PAL SCBW LOGIC LEVEL 0 1 0 1 0 1 RTCE 0 1 YGS INPI DOWN 0 1 0 1 0 1 858 total pixel clocks per line NTSC encoding (non-alternating V component) PAL encoding (alternating V component). Default after reset. enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4) standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4). Default after reset. no real time control of generated subcarrier frequency. Default after reset. real time control of generated subcarrier frequency through SAA7151B or SAA7111 (see Fig.9) luminance gain for white - black 100 IRE. Default after reset. luminance gain for white - black 92.5 IRE including 7.5 IRE set-up of black PAL switch phase is nominal. Default after reset. PAL switch phase is inverted compared to nominal DACs in normal operational mode. Default after reset. DACs forced to lowest output voltage DESCRIPTION 864 total pixel clocks per line. Default after reset.
1996 Jul 03
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Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
Table 16 Subaddress 62 DATA BYTE BSTA DESCRIPTION amplitude of colour burst; input representation in accordance with CCIR 601 CONDITIONS white-to-black = 92.5 IRE; burst = 40 IRE; NTSC encoding BSTA = 0 to 1.25 x nominal(1) white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding BSTA = 0 to 1.76 x nominal(2) white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding BSTA = 0 to 1.20 x nominal(3) white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 1.67 x nominal(4) DECTYP real time control input (RTCI) logic 0 logic 1 Notes 1. Recommended value: BSTA = 102 (66H). 2. Recommended value: BSTA = 72 (48H). 3. Recommended value: BSTA = 106 (6AH). 4. Recommended value: BSTA = 75 (4BH). Table 17 Subaddress 63 to 66 (four bytes to program subcarrier frequency) DATA BYTE DESCRIPTION CONDITIONS
SAA7184; SAA7185B
REMARKS
control from SAA7151B digital colour decoder control from SAA7111 video input processor (VIP)
REMARKS FSC3 = most significant byte FSC0 = least significant byte
FSC0 to FSC3 ffsc = subcarrier frequency f fsc 32 FSC = round ------- x 2 (in multiples of line f llc frequency); fllc = clock frequency (in see note 1 multiples of line frequency) Note 1. Examples: a) NTSC-M: ffsc = 227.5, fllc = 1716 FSC = 569408543 (21F07C1FH). b) PAL-B/G: ffsc = 283.7516, fllc = 1728 FSC = 705268427 (2A098ACBH).
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Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
Table 18 Subaddress 67 to 6A DATA BYTE(1) L21O0 L21O1 L21E0 L21E1 Note first byte of captioning data, odd field second byte of captioning data, odd field first byte of extended data, even field second byte of extended data, even field DESCRIPTION
SAA7184; SAA7185B
1. LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of line 21 encoding format. Table 19 Subaddress 6B DATA BYTE SCCLN MODIN PCREF Note 1. Line = (SCCLN + 4) for M systems; line = (SCCLN + 1) for other systems. Table 20 Logic levels and function of MODIN DATA BYTE FUNCTION MODIN1 0 0 1 1 MODIN0 0 1 0 1 unconditionally from MP port from MP port, if pin SEL_ED = HIGH; otherwise from VP port unconditionally from VP port from VP port, if pin SEL_ED = HIGH; otherwise from MP port DESCRIPTION selects the actual line, where closed caption or extended data is encoded; see note 1 defines video data of MP port or VP (DP) port to be encoded; see Table 20 0 = normal polarity of CREF for DIG TV2 compatible input signals; 1 = inverted
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Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
Table 21 Subaddress 6C DATA BYTE PRCV2 LOGIC LEVEL 0 1 ORCV2 CBLF 0 1 0 DESCRIPTION
SAA7184; SAA7185B
polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively. Default after reset polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively pin RCV2 is switched to input. Default after reset pin RCV2 is switched to output if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference Pulse that is defined by RCV2S and RCV2E, also during vertical blanking Interval). Default after reset if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization only (if TRCV2 = 1). Default after reset
1
if ORCV2 = HIGH, pin RCV2 provides a `composite blanking not' signal i.e. a reference pulse that is defined by RCV2S and RCV2E, excluding vertical blanking Interval, which is defined by FAL and LAL (PRCV2 must be LOW) if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization (if TRCV2 = 1) and as an internal blanking signal
PRCV1
0 1
polarity of RCV1 as output is active HIGH, rising edge is taken when input, respectively. Default after reset polarity of RCV1 as output is active LOW, falling edge is taken when input, respectively pin RCV1 is switched to input. Default after reset pin RCV1 is switched to output horizontal synchronization is taken from RCV1 port. Default after reset horizontal synchronization is taken from RCV2 port defines signal type on pin RCV1; see Table 22
ORCV1 TRCV2 SRCV1
0 1 0 1 -
Table 22 Logic levels and function of SRCV1 DATA BYTE AS OUTPUT SRCV11 0 0 1 1 SRCV10 0 1 0 1 VS FS FSEQ not applicable VS FS FSEQ not applicable vertical sync each field. Default after reset frame sync (odd/even) field sequence, vertical sync every fourth field (PAL = 0) or eighth field (PAL = 1) AS INPUT FUNCTION
Table 23 Subaddress 6D DATA BYTE CCEN SRCM DESCRIPTION enables individual line 21 encoding; see Table 24 defines signal type on pin RCM1; see Table 25
1996 Jul 03
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Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
Table 24 Logic levels and function of CCEN DATA BYTE FUNCTION CCEN1 0 0 1 1 CCEN0 0 1 0 1 line 21 encoding OFF enables encoding in field 1 (odd) enables encoding in field 2 (even) enables encoding in both fields
SAA7184; SAA7185B
Table 25 Logic levels and function of SRCM DATA BYTE AS OUTPUT SRCM1 0 0 1 1 SRCM0 0 1 0 1 VS FS FSEQ not applicable vertical sync each field frame sync (odd/even) field sequence, vertical sync every fourth field (FISE = 1) or eighth field (FISE = 0) FUNCTION
Table 26 Subaddress 6E to 6F DATA BYTE HTRIG DESCRIPTION sets the horizontal trigger phase related to signal on RCV1 or RCV2 input values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed increasing HTRIG decreases delays of all internally generated timing signals reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV used for triggering at HTRIG = 037H Table 27 Subaddress 70 DATA BYTE VTRIG LOGIC LEVEL - DESCRIPTION sets the vertical trigger phase related to signal on RCV1 input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines variation range of VTRIG = 0 to 31 (1FH) SBLBN 0 1 PHRES Note 1. If cross-colour reduction is programmed, it is active between FAL and LAL in both events. - vertical blanking is defined by programming of FAL and LAL vertical blanking is forced in accordance with CCIR-624 (50 Hz) or RS170A (60 Hz); note 1 selects the phase reset mode of the colour subcarrier generator; see Table 28
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20
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
Table 28 Logic levels and function of PHRES DATA BYTE FUNCTION PHRES1 0 0 1 1 PHRES0 0 1 0 1
SAA7184; SAA7185B
no reset or reset via RTCI from SAA7111 if bit RTCE = 1 reset every two lines reset every eight fields reset every four fields
Table 29 Subaddress 71 to 73 DATA BYTE BMRQ beginning of MP request signal (RCM2) values above 1715 (FISE = 1) or 1727 [FISE = 0] are not allowed first active pixel at analog outputs (corresponding input pixel coinciding with RCM2) at BMRQ = 0F9H [117H] EMRQ end of MP request signal (RCM2) values above 1715 (FISE = 1) or 1727 [FISE = 0] are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with RCM2) at EMRQ = 683H [691H] Table 30 Subaddress 77 to 79 DATA BYTE BRCV beginning of output signal on RCV2 pin values above 1715 (FISE = 1) or 1727 [FISE = 0] are not allowed first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at BRCV = 0F9H [117H] ERCV end of output signal on RCV2 pin values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at ERCV = 683H [691H] DESCRIPTION DESCRIPTION
1996 Jul 03
21
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
Table 31 Subaddress 7A DATA BYTE DESCRIPTION FLC1 0 0 1 1 FLC0 0 1 0 1
SAA7184; SAA7185B
field length control interlaced 312.5 lines/fields at 50 Hz, 262.5 lines/fields at 60 Hz (reset default) field length control non-interlaced 312 lines/fields at 50 Hz, 262 lines/fields at 60 Hz field length control non-interlaced 313 lines/fields at 50 Hz, 262 lines/fields at 60 Hz field length control non-interlaced 313 lines/fields at 50 Hz, 262 lines/fields at 60 Hz
Table 32 Subaddress 7B to 7D DATA BYTE FAL LAL DESCRIPTION first active line = FAL + 4 for M systems; = FAL + 1 for other systems, measured in lines FAL = 0 coincides with the first field synchronization pulse last active line = LAL + 3 for M systems; = LAL for other systems, measured in lines LAL = 0 coincides with the first field synchronization pulse Slave Transmitter Table 33 Slave Transmitter (slave address 89H or 8DH) REGISTER FUNCTION Status byte Table 34 No subaddress DATA BYTE VER CCRDO DESCRIPTION Version identification of the device. It will be changed with all versions of the IC that have different programming models. Current version is 100 binary. 1 = closed caption bytes of the odd field have been encoded. 0 = the bit is reset after information has been written to the subaddresses 67 and 68. It is set immediately after the data have been encoded. CCRDE 1 = closed caption bytes of the even field have been encoded. 0 = the bit is reset after information has been written to the subaddresses 69 and 6A. It is set immediately after the data have been encoded. FSQ State of the internal field sequence counter. Bit 0 (FSQ0) gives the odd/even information; odd = LOW, even = HIGH. DATA BYTE SUBADDRESS D7 - VER2 D6 VER1 D5 VER0 D4 D3 D2 FSQ2 D1 FSQ1 D0 FSQ0 CCRDO CCRDE
1996 Jul 03
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Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
handbook, full pagewidth 6
MBE737
Gv
(dB)
0 -6
-12 -18 -24
(1) (2)
-30 -36 -42 -48 -54 0 (1) SCBW = 1. (2) SCBW = 0. 2 4 6 8 10 12 f (MHz) 14
Fig.3 Chrominance transfer characteristic 1.
handbook, halfpage
2
MBE735
Gv (dB) 0
(1)
(2)
-2
-4
-6
0
0.4
0.8
1.2 f (MHz) 1.6
(1) SCBW = 1. (2) SCBW = 0.
Fig.4 Chrominance transfer characteristic 2.
1996 Jul 03
23
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
Gv handbook, full pagewidth (dB)
(4)
6 0
MBE738
(2)
-6 -12 -18 -24
(3)
(1)
-30 -36 -42 -48 -54 0 2 4 6 8 10 12 f (MHz) 14
(1) (2) (3) (4)
CCRS1 = 0; CCRS0 = 1. CCRS1 = 1; CCRS0 = 0. CCRS1 = 1; CCRS0 = 1. CCRS1 = 0; CCRS0 = 0.
Fig.5 Luminance transfer characteristic 1.
handbook, halfpage
MBE736
1
Gv (dB) 0
-1 -2
-3 -4 -5
0
2
4
f (MHz)
6
CCRS1 = 0; CCRS0 = 0.
Fig.6 Luminance transfer characteristic 2.
1996 Jul 03
24
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
CHARACTERISTICS VDDD = 4.5 to 5.5 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL Supply VDDD VDDA IDDD IDDA Inputs VIL VIH LOW level input voltage (except SDA, SCL, AP, SP and XTALI) HIGH level input voltage (except LLC, SDA, SCL, AP, SP and XTALI) HIGH level input voltage (LLC) ILI CI input leakage current input capacitance clocks operating data available I/Os at high impedance Outputs VOL VOH LOW level output voltage (except SDA and XTALO) HIGH level output voltage (except LLC, SDA, DTACK and XTALO) HIGH level output voltage (LLC) I2C-bus; VIL VIH II VOL IO TLLC tr tf tSU SDA and SCL LOW level input voltage HIGH level input voltage input current LOW level output voltage (SDA) output current VI = LOW or HIGH IOL = 3 mA during acknowledge note 2 note 2 note 2 digital supply voltage analog supply voltage digital supply current analog supply current note 1 note 1 PARAMETER CONDITIONS
SAA7184; SAA7185B
MIN.
MAX.
UNIT
4.5 4.75 - - -0.5 2.0 2.4 - - - -
5.5 5.25 170 55
V V mA mA
+0.8
V
VDDD + 0.5 V VDDD + 0.5 V 1 10 8 8 A pF pF pF
0 2.4 2.6 -0.5 3.0 -10 - 3
0.6
V
VDDD + 0.5 V VDDD + 0.5 V
+1.5 +10 0.4 -
V A V mA
VDDD + 0.5 V
Clock timing (LLC) cycle time duty factor tHIGH/TLLC rise time fall time note 3 note 4 note 3 note 3 34 40 - - 41 60 5 6 - ns % ns ns
Input timing input data set-up time (any other except SEL_MPU, CDIR, RW/SCL, A0/SDA, CS/SA, RES, AP and SP) input data hold time (any other except SEL_MPU, CDIR, RW/SCL, A0/SDA, CS/SA, RES, AP and SP) 25 6 ns
tHD
3
-
ns
1996 Jul 03
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
SYMBOL Crystal oscillator fn f/fn Tamb CL RS C1 C0 tAS tAH tRWS tRWH tDD tDF tDS tDH tACS tCSD tDAT CL tOH tOD Vo(p-p) RI RL B ILE DLE
PARAMETER
CONDITIONS -
MIN.
MAX.
UNIT
nominal frequency (usually 27 MHz) permissible deviation of nominal frequency
3rd harmonic note 5
30 +50
MHz 10-6 C pF fF pF
-50 0 8 - 1.5 -20% 3.5 -20%
CRYSTAL SPECIFICATION operating ambient temperature load capacitance series resistance motional capacitance (typical) parallel capacitance (typical) 70 - 80 1.5 +20% 3.5 +20% - - - - 142 105 - - 180 - 142
MPU interface timing address set-up time address hold time read/write set-up time read/write hold time data bus floating from CS (read) data valid from CS (read) data bus set-up time (write) data bus hold time (write) acknowledge delay from CS CS HIGH from acknowledge DTACK floating from CS HIGH notes 7 and 8; n = 7 notes 7, 8 and 9 notes 7 and 8 note 6 note 6 notes 7 and 8 note 6 note 6 9 0 9 0 75 38 9 9 112 0 75 ns ns ns ns ns ns ns ns ns ns ns
Data and reference signal output timing output load capacitance output hold time output delay time CREF in output mode 7.5 4 - 40 - 25 pF ns ns
Chroma, Y and CVBS outputs output signal voltage (peak-to-peak value) internal series resistance output load resistance output signal bandwidth of DACs LF integral linearity error of DACs LF differential linearity error of DACs -3 dB note 10 1.9 18 80 10 - - 2.1 35 - - 2 1 V MHz LSB LSB
1996 Jul 03
26
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
Notes to the Characteristics 1. At maximum supply voltage with highly active input signals.
SAA7184; SAA7185B
2. The levels have to be measured with load circuits of 1.2 k to 3.0 V (standard TTL load) and CL = 25 pF. 3. The data is for both input and output direction. 4. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%. 5. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 6. The value is calculated via equation t = t SU + t HD 7. The value depends on the clock frequency. The numbers given are calculated with fLLC = 27 MHz. 8. The values given are calculated via equation t dmax = t OD + n x t LLC + t LLC + t SU and t dmin = t OH + n x t LLC + t LLC - t HD 9. The falling edge of DTACK will always occur 1 x LLC after data is valid. 10. For full digital range, without load, VDDA = 5.0 V. The typical voltage swing is 2.0 V, the typical minimum output voltage (digital zero at DAC) is 0.2 V.
handbook, full pagewidth
tHIGH
TLLC 2.6 V 1.5 V 0.6 V
LLC clock output tHD; DAT tHIGH LLC clock input tf TLLC tr
2.4 V 1.5 V 0.8 V tSU; DAT tHD; DAT tf tr 2.0 V
input data
valid td
not valid
valid 0.8 V
tHD; DAT output data valid
2.4 V not valid valid 0.6 V
MBE742
Fig.7 Clock data timing.
1996 Jul 03
27
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
handbook, full pagewidth
LLC
CREF
VP(n)
Y(0)
Y(1)
Y(2)
Y(3)
Y(4)
DP(n)
Cb(0)
Cr(0)
Cb(2)
Cr(2)
Cb(4)
RCV2
MBE739
The data demultiplexing phase is coupled to the internal horizontal phase. The CREF signal applies only for the 16 lines digital TV format, because these signals are only valid in 13.5 MHz. The phase of the RCV2 signal is programmed to tbf (tbf for 50 Hz) in this example in output mode (BRCV2).
Fig.8 Digital TV timing.
handbook, full pagewidth
H/L transition count start 128 13
HPLL increment
4 bits reserved 0 21
5 bits reserved 0
sequence bit (1) reserved (2)
RTCI
not used in DENC2
valid invalid sample sample
8/LLC
MBE743
(1) Sequence bit: PAL = logic 0 then (R - Y) line normal; PAL = logic 1 then (R - Y) line inverted. NTSC = logic 0 then no change. (2) Reserved bits: 235 with 50 Hz systems; 232 with 60 Hz systems. (3) Only from SAA7111 decoder. (4) SAA7111 provides (22:0) bits, resulting in 3 reserved bits before sequence bit.
Fig.9 RTCI timing.
1996 Jul 03
28
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
handbook, full pagewidth
A0 tAS tAH
CSN
RWN tRWS tRWH
D(7 to 0) tDD tDF
DTACK tACS tCSD tDAT
MBE740
Fig.10 MPU interface timing (READ cycle).
handbook, full pagewidth
A0 tAS tAH
CSN
RWN tRWS tRWH
D(7 to 0) tDS tDF
DTACK tACS tCSD tDAT
MBE741
Fig.11 MPU interface timing (WRITE cycle).
1996 Jul 03
29
handbook, full pagewidth
1996 Jul 03
+ 5 V analog 0.1 F VSSD 0.1 F VSSD 0.1 F VSSD VDDD2 VDDD3 37 DAC3 35 (1) 49 67 56 48 20 75 0.62 V (p-p) (2) CHROMA 47 50 55 54 VDDA4 VrefH IOA VDDA3 VDDA2 VDDA1 VSSA VSSA 0.1 F 0.1 F VSSA VSSA 0.1 F 0.1 F 15 k VSSA 0.1 F
VSSD
Philips Semiconductors
+ 5 V digital
APPLICATION INFORMATION
10 H
1 nF
10 pF X1 27.0 MHz
10 pF
3rd harmonic
XTAL1
XTAL0
VDDD1
Digital Video Encoders (DENC2-M6)
41
40
17
30
DAC2 35 (1) 51 20 75
VSSA 1.0 V (p-p) (2) Y
digital inputs and outputs
SAA7184 SAA7185B
VSSA DAC1 35 (1) 53 12 75 1, 8, 19, 28, 35, 42, 62 VSSD1 to VSSD7 46 VrefL 52 VSSA
MGC680
1.23 V (p-p)(2) CVBS
VSSA
(1) Typical value. (2) For 100/100 colour bar.
SAA7184; SAA7185B
Preliminary specification
Fig.12 Application environment of the DENC2-M6.
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
PACKAGE OUTLINE PLCC68: plastic leaded chip carrier; 68 leads
SAA7184; SAA7185B
SOT188-2
eD y 60 61 X 44 43 Z E A
eE
bp b1 wM
68
1
pin 1 index e
E
HE A A4 A1 (A 3)
k
9
27
k1
Lp detail X
10 e D HD
26 ZD B
vM A
vMB 0 5 scale 10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.30
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
24.33 24.33 23.62 23.62 25.27 25.27 1.22 1.27 24.13 24.13 22.61 22.61 25.02 25.02 1.07
45 o
0.180 inches 0.020 0.01 0.165
0.930 0.930 0.995 0.995 0.048 0.057 0.021 0.032 0.958 0.958 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.13 0.890 0.890 0.985 0.985 0.042 0.040 0.013 0.026 0.950 0.950
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT188-2 REFERENCES IEC 112E10 JEDEC MO-047AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-03-11
1996 Jul 03
31
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all PLCC packages. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9398 510 63011). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
SAA7184; SAA7185B
Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Jul 03
32
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7184; SAA7185B
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Jul 03
33
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
NOTES
SAA7184; SAA7185B
1996 Jul 03
34
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
NOTES
SAA7184; SAA7185B
1996 Jul 03
35
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com/ps/ (1) SAA7184_85B_2 June 26, 1996 11:51 am SCA50
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands
657021/1200/02/pp36 Date of release: 1996 Jul 03 Document order number: 9397 750 00439

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